My research can be mainly divided into two parts in-network data processing and database acceleration, in both cases using reconfigurable hardware.
In-network Data Processing
I am using reconfigurable hardware to explore what kind of data processing operations are suitable and can be pushed closer to the network, in particular onto the network card. In my current project I am working in the context of RoCE (RDMA over Converged Ethernet) and looking into ways of extending it with data processing functionalities. In an earlier project I developed a complete TCP/IP stack for reconfigurable hardware. This work enabled the Caribou project where we build standalone FPGA-based microsevers. The microservers implement a key-value store and can replicate data among each other over an atomic broadcast protocol. The TCP/IP network stack is open source and available on github. Among others, the network stack is used by IBM in their cloudFPGA project.
In my research I explore how to use CPU-FPGA hybrid architectures, in particular the Intel Xeon+FPGA platform, to accelerate and extend relational databases. In our project DoppioDB we accelerate regular expressions matching by using runtime-parametrizable non-deterministic finite automatas (NFAs) implemented on the FPGA. We also extended the relational database with emerging data analytics operations, such as stochastic gradient descent (SGD) or the skyline operator.
In the following video you can see my SIGMOD presentation on accelerating pattern matching queries in hybrid CPU-FPGA architectures: